Model X3DC21E2S
Rev A
Definition of the Specifications
To guarantee the part performance in Doherty architecture, the part is specified in Doherty operation for maximum
power condition and low power condition. The following specification definition assumes the extra port extension is
deembeded from the raw S parameter and the parts is measured with Pin n connected to Port n (where n=1, 2, 3, 4).
?
Maximum power condition
Under the maximum power condition, the symmetrical Doherty architecture requires main amplifier and peak amplifier to
work at full capacity with the optimum termination (50
). The two amplifiers should deliver RF power of equal
magnitude and 90 degree phase difference. Doherty combiner functions as a coherent power combiner and supplies the
90 degree phase compensation. The following specification is defined with 50
condition.
port impedance at three ports for this
Parameter
Definition
The impedance match at
Mathematical Representation
Return Loss
the combining port to a
20log
S 11
50 ? system.
The combined power
Insertion Loss
divided by the sum of
input power under the
10log
( S
2
13
+ S 14 2
)
perfect combining
condition.
The phase difference
Phase Imbalance
between Peak-Combined
path and Main-Combined
Phase
( S 14 ( ω c ) ) – Phase ( S 13 ( ω c ) )
path at ω c = 2140MHz.
The magnitude difference
?
Amplitude Imbalance
Low power condition
between Peak-Combined
path and Main-Combined
path.
( 20log S 14
? 20log S 13 )
2
Under low power condition, the Doherty operation turns off peak amplifier and requires main amplifier to be terminated
with double of the optimum impedance (100
). With the peak port open, Doherty combiner servers as an impedance
transformer transforming 50
at combining port to 100
at main amplifier port. The following specification is defined
under the port impedance condition of Port 1 (Combining Port) 50
Port) open.
, Port 4 ( Main Amp Port) 100 and Port 3 (Peak Amp
Parameter
Definition
The impedance match of
Mathematical Representation
Return Loss
Insertion Loss
the 50 to100 ?
transformer.
The output power divided
by input power.
20log
20log
S 11
S 41
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